In this work, we have performed DC model parameter extraction and statistical process variations for 7nm node target device using industry standard BSIM-CMG model. Nanowire FET is the device architecture of choice for 7nm node due to improved short channel control and high layout density. BSIM-CMG is the surface potential based compact model for common multiple gate devices. Process variations become even worse beyond 14nm node and tend to limit chip performance and yield. In this work process variations have been modeled, starting from long to nominal gate length devices, by performing 1000 Monte Carlo simulation runs. The mean and standard deviation values obtained have been compared with 7nm target values obtained by inputs from various sources. Process variations have been applied and validated over wide range of geometries and bias conditions. Excellent agreement with the target values has been obtained.