Nanowire FET design for 7-nm SOI-CMOS technology
In this paper we present analysis on a nanowire FET specific device design issue arising from the combination of stacked nanowire configuration and use of trench silicidation in the current CMOS process. Our calibrated TCAD simulation results show for the first time that nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanowires that are higher up in the stack. For nanowires with square cross-section and 6.5nm side of the square, series resistance is shown to increase by 32% between the top and bottom most nanowire. This increase in series resistance is further shown to cause 24% decrease in linear drain current.