Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs

Abstract

An analytical model of parasitic capacitance in inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (T iox) and inserted-oxide recess (T rec), is shown using the proposed model and TCAD simulations.