In this work we demonstrate InGaAs-on-Insulator FinFETs monolithically integrated on silicon substrate using selective epitaxy in oxide cavities. Scaled FinFETs, with a gate length down to 20 nm, are fabricated following a CMOS compatible process scheme including replacement meta gate (RMG). The difference between RMG and gate-first (GF) process flows on device performance is discussed. The implementation of an RMG scheme enabled improved off-state behavior, with a 50% reduction of the subthreshold slope. RMG FinFETs with LG = 90 nm and WFIN = 40 nm, show competitive performance, and on-current of 100 µA/µm at fixed off-current of 100 nA/µm.