We describe our process for fabricating single-flux-quantum circuits for applications in communications metrology, advanced computing, and quantum information. The process flow includes four superconducting metal layers, one junction layer, one palladium-gold bias resistor layer, and a contact pad layer. Planarization using chemical-mechanical polishing is performed on the two lower insulating layers. This process is based on Josephson junctions with niobium superconducting electrodes and self-shunted, amorphous niobium-doped silicon barriers on the insulating side near the metal-insulator transition. The barrier material is deposited by cosputtering silicon and niobium, with the junction properties controlled by the relative sputtering powers and the duration of the barrier deposition step. The profiles of the deposition rates across 3-in (76.2 mm) wafers give a corresponding radial profile of the critical current density Jc that increases by ∼46% from the center to the edge of the wafer. To characterize our process, we have measured and show data for niobium metal quality and its magnetic penetration depth, as well as for wire and via inductances, and for via critical currents. The uniformity of the junction critical current Ic across a wafer was measured on test chips with 2.7-μm-diameter junctions. Within a 5 mm × 5 mm area, the standard deviation of Ic was ∼2% for chips near the center of the wafer and up to ∼7% for chips near the edge. We also describe process improvements and innovations under development aimed at increasing circuit density and high-speed performance.