Optimal design of nanoscale triple-gate devices
Meng-Hsueh Chiang, Tze-Neng Lin, et al.
IEEE SOI 2006
This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.
Meng-Hsueh Chiang, Tze-Neng Lin, et al.
IEEE SOI 2006
Keunwoo Kim, Koushik K. Das, et al.
VLSI-DAT 2007
Rajiv V. Joshi, Saibal Mukhopadhyay, et al.
IEEE Journal of Solid-State Circuits
Rouwaida Kanj, Rajiv V. Joshi, et al.
ISLPED 2008