About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ISCAS 1990
Conference paper
Partitioning logic to optimize routability on graph structures
Abstract
The problem of partitioning the nodes of a logic network (i.e., a hypergraph) on to the vertices of a partition graph G, in which the cost function to be minimized is the cost of global routing, (i.e., the cost of routing the nets of the logic on the edges of the graph G), is studied. Each vertex of the partition graph has a given upper bound on the number of nodes of the logic that can be assigned to the vertex. The nets of the logic network and the edges of the partition graph may have weights associated with them, which appear as multiplicative factors in the routing cost function. This partitioning program is called the min-cost partitioning on a graph (MCPG) problem. The MCPG model is very general and can be applied in many partitioning situations arising in VLSI physical design. Two such applications are described.