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Publication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper
On Computing the Sizes of Detected Delay Faults
Abstract
Defects in integrated circuits can cause delay faults of various sizes. Testing for delay faults has the goal of detecting a large fraction of these faults for a wide range of fault sizes. Hence, an evaluation scheme for a delay fault test must not only compute whether or not a delay fault was detected, but also calculate the sizes of detected delay faults. Delay faults have the counterintuitive property that a test for a fault of one size need not be a test for a similar fault of a larger size. This makes it difficult to answer questions about the sizes of delay faults detected by a set of tests. This paper presents a model for delay faults that answers such questions correctly, but with calculations simple enough to be done for large circuits. © 1990 IEEE