New prospects for clocking synchronous and quasi-asynchronous systems

Abstract

Through careful and innovative circuit and interconnect design, global clock distributions have been successfully constructed into the multi-GHz range. These networks include tunable trees, grids, and hybrid networks, including tree-driven grids. Modeling and design of complicated transmission line effects is required at these frequencies. Adaptive and active de-skewing circuits have also been successfully employed to compensate for process variations and (slowly-varying) temperature variations, often at the expense of degraded clock latency and increased power-supply noise sensitivity. Despite these past successes, current techniques for global clock distribution face increasing challenges in distributing low-jitter clocks in the presence of power-supply noise. Furthermore, the power dissipated by the clock network is becoming a very significant fraction of the total power demands of the chip. Resonant clocking techniques, which resonate the clock capacitance with on-chip inductance, promise to ease these constraints, enabling lower-power global clock networks with high immunity to power-supply noise. The inductance can come from on-chip wires (in the form of traveling-wave and standing-wave clocks) or spiral inductor topologies embedded into the clock wiring network. Topologies that act as either resonant loads or free-running oscillators will be described using visualizations of full-wave simulation results. Asynchronous techniques promise to eliminate clocks entirely. Proponents may argue that this eliminates issues associated with clock skew, jitter and power. We will argue a more realistic viewpoint that recognizes that asynchronous systems must still distribute "control signals." Variation in the delay of these signals (skew and jitter) presents the same synchronization overhead as clock skew and jitter in synchronous systems. Just as "synchronous" designers have borrowed and adapted many asynchronous techniques (self-timed and self-resetting circuit styles, source-synchronous links), "asynchronous" designers can benefit from understanding techniques employed by synchronous designers to distribute signals across wide areas with high precision in the presence of process, temperature, and voltage variability. While fully asynchronous high-speed processors do not seem imminent, there is a growing opportunity for significant benefit from GALS (Globally Asynchronous Locally Synchronous) concepts on multiprocessor chips. Due to uncontrollable across-chip variations in device parameters, power supply, and temperature, the optimum frequency of each processor varies independently with time. Power saving techniques such as clock gating tend to further increase these variations. There may also be different processors designed for different frequencies on the same chip. Thus the hidden costs of a single fixed cycle-time global clock are growing. For fast processors the variations are random but slow compared to the cycle time, so each processor and asynchronous interface might track them. As a result, robust low-latency asynchronous interfaces could give us many of the benefits of asynchronous design while still leveraging the huge investment in synchronous processor design, methodology, and experience.