Stefano Bianchi, Irene Muñoz-Martín, et al.
VLSI Circuits 2019
Perpendicular spin-transfer torque (p-STT) magnetic memory is gaining increasing interest as a candidate for storage-class memory, embedded memory, and possible replacement of static/dynamic memory. All these applications require extended cycling endurance, which should be based on a solid understanding and accurate modeling of the endurance failure mechanisms in the p-STT device. This paper addresses cycling endurance of p-STT memory under pulsed electrical switching. We show that endurance is limited by the dielectric breakdown of the magnetic tunnel junction stack, and we model endurance lifetime by the physical mechanisms leading to dielectric breakdown. The model predicts STT endurance as a function of applied voltage, pulsewidth, pulse polarity, and delay time between applied pulses. The dependence of the endurance on sample area is finally discussed.
Stefano Bianchi, Irene Muñoz-Martín, et al.
VLSI Circuits 2019
Stefano Ambrogio, Pritish Narayanan, et al.
VLSI-TSA 2020
Sidney Tsai, Pritish Narayanan, et al.
ISCAS 2023
Robert M. Shelby, Pritish Narayanan, et al.
EDTM 2017