Jean-Olivier Plouchart, Jonghae Kim, et al.
IEDM 2005
This letter reports the statistical analysis of circuit-level FET high-speed performance in 65-nm silicon-on-insulator CMOS technology. Practical performance metrics are derived from full 300-mm wafer measurements. The proposed circuit-level layout wiring parasitics-aware FET reflects realistic FET that is placed in circuits. Its measurement and model are directly applicable to circuit design in conjunction with multiple layers of yield and manufacturability considerations. A stretched gate-pitch NFET design shows an average current gain cutoff frequency fT of 250 GHz, with 7.6% standard deviation, 6.7% mismatch standard deviation, and maximum fT of 307 GHz. The proposed characterization methodology will become more relevant to technologies beyond 65 nm. © 2007 IEEE.
Jean-Olivier Plouchart, Jonghae Kim, et al.
IEDM 2005
Daeik D. Kim, Jonghae Kim, et al.
ISSCC 2007
Daeik Kim, Jonghae Kim, et al.
IEEE Electron Device Letters
Wooram Lee, Caglar Ozdag, et al.
IEEE Journal of Solid-State Circuits