Publication
IEEE Magnetics Letters
Paper

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

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Abstract

Binary stochastic neurons (BSNs) form an integral part of many machine learning algorithms, motivating the development of hardware accelerators for this complex function. It has been recognized that hardware BSNs can be implemented using low-barrier magnets (LBMs) by minimally modifying present-day magnetoresistive random-access memory (MRAM) devices. A crucial parameter that determines the response of these LBM-based BSN designs is the correlation time of magnetization \tau -c. In this letter, we show that, for magnets with low-energy barriers (\Delta \approx k-BT and below), circular disk magnets with in-plane magnetic anisotropy (IMA) lead to \tau -c values that are two orders of magnitude smaller than \tau -c of magnets with perpendicular magnetic anisotropy (PMA). Analytical descriptions demonstrate that this striking difference in \tau -c is due to a precessionlike fluctuation mechanism that is enabled by the large demagnetization field in IMA magnets. We provide a detailed energy-delay performance evaluation of previously proposed BSN designs based on spin-orbit torque MRAM and spin-transfer torque MRAM employing low-barrier circular IMA magnets by SPICE simulations. The designs exhibit subnanosecond response times leading to energy requirements of approximately a few femtojoules to evaluate the BSN function, orders of magnitude lower than digital CMOS implementations with a much larger surface area. While modern MRAM technology is based on PMA magnets, results in this letter suggest that low-barrier circular IMA magnets may be more suitable for this application.

Date

01 Jan 2019

Publication

IEEE Magnetics Letters

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