Issues in multi-level cache designs

Abstract

Due to the rapid growth of processor speeds and the expansion of application base, multi-level cache hierarchies are becoming more important for microprocessor systems. One classical technique in designing multi-level caches is the subset-rule, with which the cache contents at a hierarchy are maintained as subset of the next level hierarchy. A major benefit of subset-rule is the conceptual simplicity for cache coherence control. However, in certain systems conventional sub-set management may result in higher hardware costs or in unexpected performance losses. In this paper we investigate these aspects through simulations for a multiprocessor environment. Several alternatives to the conventional subset approach are proposed and evaluated. We also examine some new techniques for managing coherence information at lower costs when very large caches are involved.