Arun Viswanathan, Nancy Feldman, et al.
IEEE Communications Magazine
An investigation of trap states at the semiconductor-oxide interface of single silicon nanowires is presented using vertical gateall-around nanowire MOS capacitors. By performing highly accurate capacitance-voltage measurements at room temperature, the energetic distribution of interface traps Dit could be extracted with the quasi-static method. Although the capacitance of a single nanowire MOS capacitor with Al2O3 gate oxide is only 2 fF, Dit values were obtained with good reproducibility. For etched, vertical Si nanowires, Dit in the range of (4 ± 1) × 1012 cm-2eV-1 was obtained. © 2002-2012 IEEE.
Arun Viswanathan, Nancy Feldman, et al.
IEEE Communications Magazine
Thomas R. Puzak, A. Hartstein, et al.
CF 2007
György E. Révész
Theoretical Computer Science
G. Ramalingam
Theoretical Computer Science