Publication
ASICON 2017
Conference paper

Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS

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Abstract

In this paper, we discuss a technique for selective GeOx-scavenging which creates a GeOx-free interfacial layer (IL) on Si1-xGex substrates. This process reduces interface trap density (Nit) and increases high-field hole mobility in Si1-xGex pFETs. In addition, we identify the existence of electronic defect levels close to the Si1-xGex band edges associated with the Ge surface concentration at the Si1-xGex/IL interface. These electronic defects act as carrier scattering centers severely degrading the channel mobility and modulate the device threshold voltage. By successfully eliminating the GeOx component in the IL and electronic defects states at the Si1-xGex/IL interface, high channel carrier mobility over a wide range of inversion carrier density in compressively-strained Si1-xGex channel pFETs is demonstrated.

Date

01 Jul 2017

Publication

ASICON 2017

Authors

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