About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
EPEPS 2008
Conference paper
Impedance design for multi-layered vias
Abstract
This paper presents a methodology based on a semi-analytical scattering model to pre-design the characteristic impedance of multi-layered through hole vias by choosing appropriate via geometrical parameters, dielectric property, and the placement of ground vias. A linear model as a function of design parameters above is further applied to analyze the statistical variation of impedance for different tolerance specification. © 2008 IEEE.