Anupam Gupta, Viswanath Nagarajan, et al.
Operations Research
The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met. © 2007 IBM.
Anupam Gupta, Viswanath Nagarajan, et al.
Operations Research
Michael Ray, Yves C. Martin
Proceedings of SPIE - The International Society for Optical Engineering
Arun Viswanathan, Nancy Feldman, et al.
IEEE Communications Magazine
S. Sattanathan, N.C. Narendra, et al.
CONTEXT 2005