Lerong Cheng, Jinjun Xiong, et al.
ASP-DAC 2008
The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met. © 2007 IBM.
Lerong Cheng, Jinjun Xiong, et al.
ASP-DAC 2008
Robert E. Donovan
INTERSPEECH - Eurospeech 2001
Daniel Bauer, Luis Garcés Erice, et al.
VLDB 2026
Oliver Bodemer
IBM J. Res. Dev