Hybrid number system multiplier for graphics and complex arithmetic applications

Abstract

A hybrid multiplier design which supports 32-bit floating-point, 24-bit fixed-point and 32-bit logarithmic number systems is described. Except for additions and subtractions, floating-point operations such as multiplication, division, and square root are all performed in the logarithmic number system domain. A modified squaring approach is adopted for fixed-point multiplications with little extra hardware. The performance of this multiplier is shown to be superior to that of conventional binary multipliers for most graphics and digital signal processing applications, and the size of the multiplier is comparable to that of conventional multipliers in terms of silicon area.