High-Speed Low-Power ECL Circuit with AC-Coupled Self-Biased Dynamic Current Source and Active-Pull-Down Emitter-Follower Stage

This paper presents an ECL circuit with ac-coupled self-biased dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array applications. The circuit features an ac-coupled dynamic current source to improve the power-delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-pm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.62 X (1.90 X) improvement in the speed (load driving capability) of a loaded gate compared with the conventional ECL circuit. The design considerations of the circuit are discussed. © 1992 IEEE