A high performance low temperature 0.3 μm CMOS on SIMOX
G. Shahidi, B. Bucclot, et al.
VLSI Technology 1992
Devices have been designed and fabricated for a CMOS technology with the nominal channel length of 0.15 μm and minimum channel length below 0.1 μm. In order to minimize short-channel effects (SCE’s) down to channel lengths below 0.1 μm, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF implant) were used. Maximum high Vthreshold rolloff was 250 mV at effective channel length of 0.06 μm. For the minimum channel length of 0.1 μm, the loaded (FI = FO = 3, C= 240 fF) and unloaded delays were 150 and 25 ps, respectively. © 1993 IEEE
G. Shahidi, B. Bucclot, et al.
VLSI Technology 1992
R.V. Joshi, W. Hwang, et al.
IEEE International SOI Conference 1998
F. Assaderaghi, G. Shahidi
IEEE International SOI Conference 2000
Rouwaida Kanj, Rajiv Joshi, et al.
ICCAD 2009