Publication
ESTC 2016
Conference paper

Exploration of inductor-based hybrid integrated voltage regulator architectures

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Abstract

Integrated voltage regulators (IVRs) fabricated and positioned close to the microprocessors can improve the energy conversion efficiency, power density and the output voltage regulation performance compared to discrete VRs. The highest cost in terms of space and volume in such IVRs corresponds to the bulky passive components needed for their operation. In this paper, two different hybrid architectures for IVRs are considered and evaluated. The proposed voltage regulators consist of a four-phase interleaved buck converter operated in Continuous Conduction Mode (CCM). The rated power of the considered converter is 1W, and nominal input and output voltages are constant and equal to Vin = 1.7V and Vout = 0.85V, respectively. In one case, inductors and deep trench capacitors are microfabricated in a silicon interposer underneath the CPU chip. In the second case, discrete off-the-shelf inductors and capacitors are assembled in the chip carrier laminate substrate. In both cases, the active components, i.e., the power switches and driving circuits for the buck converter in a half-bridge configuration (four phases) are fabricated using using 32nm CMOS process (IBM) in a power management IC (PMIC). This IC forms the test platform for the demonstration of the proposed hybrid integrated voltage regulator (HIVR), and also contains a CMOS programmable resistive load to emulate the CPU. The efficiency, power density and other performance metrics of both implementations are evaluated using modeling and simulations. Results from our design analyses show that while the laminate implementation fares well with regard to efficiency (≃ 93.5%), it cannot reach the high power densities attainable in the interposer implementations ≃ 0.95W/mm2.

Date

01 Dec 2016

Publication

ESTC 2016

Authors

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