Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
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6 results for Indira Seshadri
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- Indira Seshadri
- Eric Miller
- et al.
- 2023
- IEDM 2023
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022
EUV patterned gate variation reduction in next generation transistor architectures
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Nanosheet Metrology Opportunities for Technology Readiness
- Mary Breton
- Daniel Schmidt
- et al.
- 2021
- SPIE Advanced Lithography 2021
Etch and Patterning Development for 2nm Node Nanosheet Devices
- Eric Miller
- Indira Seshadri
- et al.
- 2022
- SPIE Advanced Lithography 2022