Efficient Prediction of Equalization Effort and Channel Performance for PCB-Based Data Links

Abstract

High-speed data links that utilize multilayer printed circuit boards suffer from loss, dispersion, and intersymbol interference. Often, equalization and error correction are required to make these channels functional at gigabit data rates and demand costly analyses. The characterization of loss-dominated links can be generalized and simplified by means of a normalized link length as presented herein. Based on a correlation of this normalized length and observed eye opening, a novel assessment of wired digital links for frequencies up to 50GHz and data rates up to 30 Gb/s is proposed. It allows for an efficient prediction of the amount and type of required equalization for a given link as well as determining maximum tolerable loss for a given equalizer configuration. The proposed method and its applicability are demonstrated by means of practical examples.