Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays

Abstract

This paper deals with the issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed in this paper consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. We first consider an array grid model based on single-track switches for which simulations performed by previous researchers have shown that considerable enhancement in yield can be achieved by reconfiguring arrays according to a set of conditions that can be formally stated in the form of a so-called reconf igurability theorem. However, the important issue of developing efficient algorithms for determining whether the conditions in the reconfigurability theorem are met has not been resolved, and the algorithms proposed in the literature to do so are of exponential complexity. In this paper, we resolve this open problem by proposing an efficient polynomial time algorithm for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, we also show that the set of conditions in the reconfigurability theorem is not necessary. Finally, we develop a polynomial time algorithm for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switches. © 1990 IEEE