Effect of hot carrier stress on device junctions measured by electron holography and scanning capacitance microscopy

Abstract

The effect of hot carrier injection on the FET's junction properties has been investigated for CMOS NFET devices. Junction profiles and carrier concentration of stressed and unstressed devices are measured and compared by dual lens electron holography and scanning capacitance microscopy, respectively. The measurements reveal that the width of the junction on the drain side of the device that undergoes hot carrier stressing decreases, indicating a reduction in active carrier concentration. These results are consistent with the hypothesis of phosphorous dopant passivation by the hot carrier induced release of hydrogen into the drain side extension region.