High NA EUV lithography will offer single exposure patterning for pitches below 28nm, simplifying process flows. However, overlay error complexity will increase. Specifically, a semiconductor build will require use of both high NA EUV tools that can only expose half the field size of low NA EUV and optical tools. This means that to achieve full productivity on the low NA EUV and optical tools used, a semiconductor build using these tools will need to minimize overlay error back to a scanner map exposed with the high NA EUV tool that has twice the number of exposures. Overlay error minimization on full field tools takes advantage of keeping exposure maps constant between different layers so that scan direction and step direction are maintained. This is not possible when using a high NA EUV tool in a semiconductor build unless the number of scans on the low NA and optical tools are doubled, thus decreasing the productivity on those tools. Having a full field minimize overlay error back to two half fields results in new required overlay controls between the two half fields to achieve low overlay error. In particular, stitch overlay control for the half field exposures can be very helpful to achieving good overlay error between a layer exposed with full field exposure map and a layer exposed with a half field exposure map. To get early learning on these effects, we designed a test reticle with a unique "figure 8"black border that allows step plans to be exposed with either half or full field exposures. To get rapid learning the reticle is designed to take advantage of resist-to-resist overlay targets that engage with each other when there is a programed 180 um step delta between the two exposures. The effects of order of exposures as well as scan and step direction differences between the half field and full field step plans are investigated.