IEEE Journal of Solid-State Circuits

Digital FIR Filters for High Speed PRML Disk Read Channels

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This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology. © 1995 IEEE