MRS Fall Meeting 2008
Conference paper

Die-to-wafer 3D integration technology for high yield and throughput


Three-Dimensional (3D) devices are attractive to overcome serious interconnect scaling problems and extend the CMOS performance roadmap. It also offers possibilities for integrating different components using various technologies that reduce the process complexity and increase the functionality. This paper illustrates different 3D integration approaches such as die-to-die, die-to-wafer, and wafer-to-wafer. We describe a die cavity technology for die-to-wafer integration with high yield and throughput, followed by a description of the key process technology elements which are needed for 3D integration, and then cover 3D test vehicle fabrication and assembly. Results demonstrate that multiple 70μm thick dies with through silicon vias (TSVs) at multiple locations can be successfully stacked on a wafer using lead-free solder interconnections in a single bonding step. Thermal reliability testing was done and the resistances of the TSVs and lead-free solder interconnects were monitored up to 1,000 cycles with no failures occurring. © 2009 Materials Research Society.