Device, Circuit, and Technology Scaling to Micron and Submicron Dimensions

Abstract

From the discrete semiconductor component technology of the early 1960's, where the transition from the past focused on a major reduction in device size, i.e., from vacuum tubes to transistors, the emphasis from the late 1960's to the present has centered on integrating an ever-increasing number of devices on a chip. This trend has given rise to the acromyms SSI, MSI, LSI, and VLSI standing for small scale, medium scale, large scale, and very large scale integration, respectively. Following a discussion of the trends in device integration levels, four topics impacting our ability to achieve these levels are discussed from technological and engineering points of view. These are shrinking of conductor and device dimensions, known as scaling, reliability concerns in small structures, representative processes utilized in achieving small structures, and anticipated circuit delays for Insulated-Gate Field-Effect Transistors, IGFET's, at 1-μm design groundrules. The problems are numerous, and the potential solutions are even more numerous. However, it is not unreasonable to expect that these can all be sorted out during the 1980's. If this comes to pass, the one can expect IGFET integration levels of 106 bits of dynamic random-access memory, DRAM, storage on a 70-mm2 chip, and logic circuit performance at the 1-ns level at room temperature and <0.5 ns at liquid nitrogen temperature. The logic numbers are in the context of maximum performance achievable at maximum circuit density, and at an acceptable power dissipation level of 2 W/chip or less (where the chip area is between 0.2 and 0.3 cm2). Copyright © 1983 by The Institute of Electrical and Electronics Engineers, Inc.v