Design Tools for Resistive Crossbar based Machine Learning Accelerators

Abstract

Resistive crossbar based accelerators for Machine Learning (ML) have attracted great interest as they offer the prospect of high density on-chip storage as well as efficient in-memory matrix-vector multiplication (MVM) operations. Despite their promises, they present several design challenges, such as high write costs, overhead of analog-To-digital and digital-To-Analog converters and other peripheral circuits, and accuracy degradation due to the the analog nature of in-memory computing coupled with device and circuit level non-idealities. The unique characteristics of crossbar-based accelerators pose unique challenges for design automation. We outline a design flow for crossbar-based accelerators, and elaborate on some key tools involved in such a flow. Specifically, we discuss architectural estimation of metrics such as power, performance and area, and functional simulation to evaluate algorithmic accuracy considering the impact of non-idealities.