IEDM 2004
Conference paper

Charge trapping in aggressively scaled metal gate/high-κ stacks


A comparative analysis of charge trapping in advanced metal gate/high-κ stacks with EOT below 1 nm (corresponding to CETs, or T inv, in the 1.2 - 1.5 nm range) has been carried out. We investigate the effects of: (i) gate electrode material (namely, various metals vs. fully suicided gates (FUSI) vs. conventional poly-Si gates), (ii) high-κ dielectric material (HfO2, HfO2:N, HfSiO, HfSiON, ZrO 2, Al2O3); (iii) high-κ deposition technique (MOCVD vs. ALD), (iv) bottom interface; and (v) annealing effects, both postdeposition (PDA) and in a forming gas (FGA). Significant improvement of charge trapping in all Me-gate stacks has been consistently demonstrated. Based on this systematic analysis, we come to a conclusion that interaction(s) between the high-κ layer and poly-Si plays a major role in charge trapping degradation. © 2004 IEEE.