C4NP - First manufacturing & reliability data for high-end FlipChip solder bumping based on IBM's C4NP process

Abstract

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies used are FlipChip in Package (FCiP) and Wafer Level Chip Scale Package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC Board (PCB). WLCSP devices connect directly onto the board. There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres. FCiP demands many small bumps on tight pitch whereas WLCSP typically requires much larger solder bumps. All these established technologies have important limitations for fine pitch bumping especially when it comes to lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially when it comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry.