Abstract
To meet the European Union Restriction of Hazardous Substances requirements and the continuing demand for lower costs, finer pitch, and high-reliability flip-chip packaging structures, considerable work is going on in the electronic industry to develop lead-free solutions for flip-chip technology. In this paper various solder-bumping technologies developed for flip-chip applications are reviewed with an emphasis on a new wafer-bumping technology called C NP (Controlled-Collapse-Chip-Connect New Process). Several inherent advantages of C NP technology are discussed over other technologies. This paper will also discuss the recent development and implementation of lead-free C interconnections for 300 mm wafers demonstrated at IBM. In addition, some metallurgical considerations associated with C NP technology are discussed.