Publication
Microprocessing and Microprogramming
Paper

Array processor for LS FIR system identification

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Abstract

In this paper the architecture for the realization of a new, highly parallel, block-type, order recursive algorithm for LS FIR system identification is presented. This algorithm is intended either for processing a single block data or for a block adaptive mode of operation and it can track variations from block to block. A linear array of O(p) processing elements is used, implementing this algorithm in O(p) time units. Using a suitable sequencing of the equations of the algorithm and a pipelined divider a three fold reduction of hardware is achieved, without significant degradation in time performance, compared to the fully parallel realization. Furthermore, the computation of the correlation sums, needed for initialization purposes, is performed on the existing linear array resulting in additional hardware saving. © 1991.

Date

01 Jan 1991

Publication

Microprocessing and Microprogramming

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