High quality image reconstruction algorithms are of special importance for tomographic applications. This paper presents the register transfer level and the VLSI design of a special purpose array processor which realizes a tomographic algorithm having higher quality reconstructions than other well-known algorithms. The operation of the array processor is pipelined and, most important, the communication delays have been eliminated by overlapping arithmetic and logic operations with data transfer. The design and operation of the array processor, which fully exploits the special features of the algorithm to optimize the units and subunits, leads to high hardware utilization. In contrast to other attempts, the number of units is limited resulting in a reasonable sized hardware system achieving real-time reconstruction. The paper presents some important performance analysis of the proposed architecture. © 1992.