Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wire connections. Second, we build and validate effective TSV models for current density distributions. Finally, these models are integrated with global power wires for detailed chip-scale power grid analysis. © 2012 ACM.