An Integrated Environment for Technology Closure of Deep-Submicron IC Designs

Abstract

The utilization of timing closure based integrated technology in the manufacturing of deep-submicron integrated circuit (IC) designs is discussed. As interconnect delay dominates the overall chip performance, achieving of accurate timing optimization and delay prediction is inherent for improving circuit performance. IBM's Place-Driven Synthesis (PDS) system describes an effective flow for achieving technology closure. The prerequisites for the PDS system and timing-driven placement and logic optimization, which include buffering and resizing optimization, are discussed.