Technology impacts on sub-90nm CMOS circuit design & design methodologies

Abstract

This tutorial discusses design challenges of scaled CMOS circuits in sub-90nm technologies and the design methodologies required to design them in order to produce robust designs with desired power performance trade-off. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines. On the technology front, the question arises whether we can continue along the traditional CMOS scaling path - reduce effective oxide thickness, improve channel mobility, and minimize parasitics. On the design front, researchers are exploring various circuit design techniques to deal with process variation, leakage and soft errors. We will focus on the following components: Design challenges of sub-90nm CMOS circuits with particular emphasis on implications of each individual device scaling element on circuit design: To continue scaling of the CMOS devices deep into sub-90nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process variations. As the scaling approaches various physical limits, new design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher Vt,lin to maintain adequate Vt,sat, continue to surface. In this part of tutorial, we will discuss these emerging trends and design issues related to aggressive device scaling. Managing leakage power: It is well known that with CMOS technologies beyond 90nm, leakage power is one of the most crucial design components which must be efficiently controlled in order to utilize the performance advantage from these technologies. We will focus on various techniques to analyze and control all components of leakage power placing particular emphasis on sub-threshold and gate leakage power. In addition, this part of tutorial will discuss low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, well biasing techniques, and design of low leakage data-paths and caches. Circuit Design in the Presence of Uncertainty: Nanometer design technologies must work under tight operating margins, and are therefore highly susceptible to any process and environmental variabilities. This part of the tutorial will consider several factors related to reliability and yield. With regard to environmental variations, it is important to build circuits that have well-distributed thermal properties, and to carefully design supply networks to provide reliable Vdd and ground levels throughout the chip. On the process variation front, the effects of uncertainties in process variables must be modeled using statistical techniques, and they must be utilized to determine variations in the performance parameters of a circuit. Instead of pessimistically treating timing in a worst-case manner as is conventionally done in static timing analysis, statistical techniques will have to be employed that directly predict the percentage of circuits that are likely to meet a timing specification. Parameter Variation Tolerance: We will cover the components of variation and some circuit techniques to address variation tolerance. Process variation has also received increased attention from design automation community. Traditional sources of variation due to circuit and environmental factors also affect circuit performance significantly. These are cross capacitance, power supply integrity, multiple input switching, errors arising due to tools and flows, etc. We will present these sources and quantify their impact on high-speed microprocessor performance. Radiation-induced single event upsets (SEUs): Soft errors pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Soft errors and single event upsets are gaining increased attention as the technology scales. Measured data shows 8% soft error rate (SER) increase per bit per technology generation. As the number of memory bits and sequential elements increases across generations, the soft error problem is likely to become a serious barrier for advanced microprocessors. Historically, we have considered power-performance-area tradeoffs. There is a need to include the SER as another design parameter. In this tutorial, we also present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SER using a high-intensity neutron beam, the characterization of SER in sequential logic cells, and technology scaling trends. Circuit techniques for soft error tolerance are also presented with their relative benefit. © 2006 IEEE.