VLSI Technology 1993
Conference paper

A room temperature 0.1 μm CMOS on SOI

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An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick non-delpleted (0.1μm) SOI film, highly non-uniform channel doping and source-drain extension-HALO were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. Very high speeds were obtained: Unloaded delay was 20 psec, and fully loaded NAND (FI=FO=3, CL=0.3 pF) delay was 130 psec at supply of 1.8 V.