About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IMW 2011
Conference paper
A novel reconfigurable sensing scheme for variable level storage in phase change memory
Abstract
This paper presents a novel reconfigurable sensing scheme with the flexibility to change reading precision of analog resistance levels for MLC PCM. A 2Mcell PCM chip was fabricated in 90nm CMOS technology and was tested. Operating at 8-bits precision (adequate for 7b/cell PCM i.e., 128 resistance levels), read access latency is 5μs (measured at 50MHz clock), compared to 35-50μs in state-of-art 2b/cell NAND Flash. © 2011 IEEE.