A new approach to the hardware implementation of high-speed processors dedicated to perform the fast Fourier transform (FFT) in real time is presented. This approach capitalizes on recent advances in semiconductor memory technology to eliminate conventional multipliers, and is shown to offer significant reductions in hardware complexity and power consumption. It also yields a highly modular hardware configuration. A modified floating-point arithmetic is incorporated to allow a wider dynamic range. Using standard available TTL integrated circuits, a throughput of complex data points at a 25 MHz word rate is possible. © 1975, IEEE. All rights reserved.