VLSI Technology 1992
Conference paper

A high performance BiCMOS technology using 0.25 μm CMOS and double poly 47 GHz bipolar

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By merging a 0.25 /an CMOS proccss and a 0.4 //m emitter width, 47 GHz fT self-aligned bipolar process, a high performance BiCMOS technology has been developed. Decoupling of the CMOS and bipolar fabrication steps allows optimum process conditions for both the bipolar and the CMOS. CMOS ring oscillators with 50 psec delay per stage at 2.5 volt supply, ECL ring oscillator delays of 48 psec at 1.2 niA, and fast loaded BiNMOS gate delays arc demonstrated.