A 640-ps, 0.25-μm CMOS, 16 × 64-b three-port register file

Abstract

We describe a 640-ps read access, 16-word by 64-b, three-port register file fabricated in 0.25-μm effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate register file operations at 625 MHz. Additionally, internal probe measurements of the read access path components are presented and compared with circuit simulations.