A 250-Mbit/s Cmos Crosspoint Switch

Abstract

Voltage swing reduction and constant current steering techniques for high-speed CMOS crosspoint switches are described. These techniques reduce crosstalk and intersymbol interference originating from capacitive and inductive couplings along the high-speed channels. An experimental 16×16 crosspoint switch employing the techniques has achieved a worst-case data rate of 250 Mbit/s with 80-percent eye opening and 0.2-ns timing jitter from a 5-V supply. The worst crosstalk noise is 140 mVp_p, average delay through the switch is 6 ns, and power consumption is 900 mW. Also, the scaling experiment has demonstrated robustness of the design against blind scaling. ©1989 IEEE