Sungjae Lee, J. Johnson, et al.
VLSI Technology 2012
Conference paper
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
Abstract
A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands. © 2012 IEEE.
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