Timothy O. Dickson, Yong Liu, et al.
CICC 2014
A 6b 10 tap-full rate distributed arithmetic digital finite impulse response filter (DFIR) is reported using dynamic logic datapath with independent precharge and compute signals per domino stage. The basic architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. Two 8b 16-entry loadable tables contain the precomputed partial sums used by the distributed arithmetic algorithms.
Timothy O. Dickson, Yong Liu, et al.
CICC 2014
Sergey Rylov, Alexander Rylyakov
BCTM 2003
Mark Ferriss, Alexander Rylyakov, et al.
VLSI Circuits 2013
Mark Ferriss, Jean-Olivier Plouchart, et al.
IEEE JSSC