Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A 1.3 Gsample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

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A 6b 10 tap-full rate distributed arithmetic digital finite impulse response filter (DFIR) is reported using dynamic logic datapath with independent precharge and compute signals per domino stage. The basic architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. Two 8b 16-entry loadable tables contain the precomputed partial sums used by the distributed arithmetic algorithms.