3D opto-electrical device stacking on CMOS

We report on the 3D integration and interconnect of top-emitting VCSEL and photodiode (PD) arrays on a CMOS substrate. This technology represents a radically new way to increase the I/O bandwidth of processors and enables a path beyond 10 Tb/s I/Os by using a high level of integration of opto-electrical devices (OED) directly on the processor. The integration process developed includes an OED placement of better than 5 μm, OED thinning down to 25 μm, and an interconnect technology with copper vias into the planarization polymer. Although the process is fully compatible with the back-end-of-line of CMOS, the experiments performed were done on dummy CMOS wafers. The opto-electrical characterization performed revealed a minimal impact of the integration process on the OED performance, demonstrating the high potential of the concept. © 2009 Elsevier B.V. All rights reserved.