IEEE Journal of Solid-State Circuits

3-D silicon integration and silicon packaging technology using silicon through-vias

View publication


System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposera with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 μm) interconnection is described. This silicon carrier package contains silicon through-vias and offers > 16 x increase over standard chip I/O, a 20 x to 100 x increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip." © 2006 IEEE.