Conference paper

15 Kb 1.5 ns Access on-chip tag SRAM


A 1.5 ns access, 15 Kb (4×128×30 b) tag SRAM macro capable of cycling at 500 MHz is presented. It is designed for 4-way set-associative cache controller application in a S/390 microprocessor. It features write-through with independent R/W control within each set, and programmable BIST (built-in self-test) capability at cycle speed. The core circuit techniques involved self-resetting CMOS (SRCMOS) for fast access/cycle time, mixed with `handshaking' between timing critical blocks to guarantee proper operating margins. A testchip was implemented in a 0.25 μm (Leff) CMOS technology with M0 and 3 layers of metal for wiring. Successful hardware operation was achieved over a wide range of supply voltages and temperature.