0. 5 MICRON GATE CMOS TECHNOLOGY USING E-BEAM/OPTICAL MIX LITHOGRAPHY.

Abstract

In the past decade, CMOS technology has been continuously scaled down to improve the performance and to increase the circuit density. The electron beam direct writing technique offers the advantage of excellent linewidth and alignment control. However, it is limited by the low wafer exposure throughput due to the inherent serial process of the electron beam. A high-performance CMOS technology using e-beam/optical mix lithography for VLSI applications is reported. Both FET devices are designed for half-micron channel lengths. N plus poly gate on 125-angstrom gate oxide and shallow source/drain junctions are used for both N and P channel devices. Self-aligned silicide is formed on source, drain and gate in order to reduce the sheet resistance. Latch-up is effectively suppressed using a retrograde N-well on a thin P-epi over a P plus substrate.